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LTC3556 1 3556p electrical specifications subject to change typical application features applications description high ef ciency usb power manager with dual buck and buck-boost dc/dcs the ltc ? 3556 is a highly integrated power management and battery charger ic for li-ion/polymer battery applica- tions. it includes a high ef? ciency current limited switching powerpath manager with automatic load prioritization, a battery charger, an ideal diode, and three synchronous switching regulators (two bucks and one buck-boost). designed speci?cally for usb applications, the LTC3556s switching power manager automatically limits input cur- rent to a maximum of either 100ma or 500ma for usb applications or 1a for adapter-powered applications. the LTC3556s switching input stage transmits nearly all of the 2.5w available from the usb port to the system load with minimal power wasted as heat. this feature allows the LTC3556 to provide more power to the application and eases the constraint of thermal budgeting in small spaces. the two buck regulators can provide up to 400ma each and the buck-boost can deliver 1a. the LTC3556 is available in the low pro? le 28-pin (4mm 5mm 0.75mm) qfn surface mount package. high ef? ciency powerpath manager, dual buck, buck-boost and ldo power manager n high ef? ciency switching powerpath tm controller with bat-track tm adaptive output control n programmable usb or wall current limit (100ma/500ma/1a) n full featured li-ion/polymer battery charger n instant-on operation with a discharged battery n 1.5a maximum charge current n internal 180m ideal diode plus external ideal diode controller powers load in battery mode n low no-load i q when powered from bat (<30a) dc/dcs n dual high ef? ciency buck dc/dcs (400ma/400ma i out ) n high ef? ciency buck-boost dc/dc (1a i out ) n all regulators operate at 2.25mhz n dynamic voltage scaling on two buck outputs n i 2 c control of enables, mode, two v out settings n enall pin with power-up sequence control n low no-load quiescent current: 20a each n hdd-based mp3 players, pdas, gps, pmps n other usb-based handheld products l , lt, ltc and ltm are registered trademarks of linear technology corporation. powerpath and bat-track are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 6522118 and 6404251. li-ion pgoodall 0.8v to 3.6v/400ma 3.3v/25ma 2.5v to 3.3v/1a 0.8v to 3.6v/400ma optional 0v t to other loads + LTC3556 dual high efficiency bucks high efficiency buck-boost i 2 c port always on ldo memory core p rtc/low power logic hdd/io 3556 ta01 usb/wall 4.5v to 5.5v charge i 2 c usb compliant step-down regulator cc/cv battery charger seq enall 3 1 2 3 battery charge current vs battery voltage battery voltage (v) 2.8 0 charge current (ma) 200 3.2 3.6 3.8 100 700 400 500 600 300 3 3.4 4 4.2 3556 ta01b battery charge current 500ma usb current limit extra current for faster charging v bus = 5v 5x mode battery charger programmed for 1a
LTC3556 2 3556p pin configuration absolute maximum ratings v bus (transient) t < 1ms, duty cycle < 1% .. C0.3v to 7v v in1 , v in2 , v in3 , v bus (static), dv cc , fb1, fb2, ntc, bat, enall, scl, sda, pgoodall, chrg ....................................... C0.3v to 6v seq ....................C0.3v to lesser of 6v or (v out + 0.3v) fb3, v c3 .............. C0.3v to lesser of 6v or (v in3 + 0.3v) i clprog ....................................................................3ma i pgoodall , i chrg ....................................................50ma i prog ........................................................................2ma i ldo3v3 ...................................................................30ma i sw1 , i sw2 ............................................................600ma i sw , i bat , i vout .............................................................2a i swab3 , i swcd3 , i vout3 .............................................2.5a operating temperature range (note 2).... C40c to 85c junction temperature (note 3) ............................. 125c storage temperature range ................... C65c to 125c (note 1) 9 10 top view 29 ufd package 28-lead (4mm s 5mm) plastic qfn 11 12 13 28 27 26 25 24 14 23 6 5 4 3 2 1 ldo3v3 clprog ntc sw1 v in1 fb1 fb3 v c3 gate chrg prog sw2 v in2 fb2 sda pgoodall enall seq sw v bus v out bat swab3 dv cc v in3 v out3 scl swcd3 7 17 18 19 20 21 22 16 8 15 t jmax = 125c, ja = 37c/w exposed pad (pin 29) is gnd, must be soldered to pcb electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v bus = 5v, v in1 = v in2 = v in3 = v out3 = 3.8v, bat = 3.8v, dv cc = 3.3v, r prog = 1k, r clprog = 3.01k, unless otherwise noted. order information lead free finish tape and reel part marking package description temperature range LTC3556eufd#pbf LTC3556eufd#trpbf 3556 28-lead (4mm 5mm) plastic qfn C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ symbol parameter conditions min typ max units powerpath switching regulator v bus input supply voltage 4.35 5.5 v i buslim total input current 1x mode, v out = bat 5x mode, v out = bat 10x mode, v out = bat suspend mode, v out = bat l l l l 87 436 800 0.31 95 460 860 0.38 100 500 1000 0.50 ma ma ma ma i vbusq v bus quiescent current 1x mode, i out = 0ma 5x mode, i out = 0ma 10x mode, i out = 0ma suspend mode, i out = 0ma 7 15 15 0.044 ma ma ma ma h clprog (note 4) ratio of measured v bus current to clprog program current 1x mode 5x mode 10x mode suspend mode 224 1133 2140 11.3 ma/ma ma/ma ma/ma ma/ma
LTC3556 3 3556p symbol parameter conditions min typ max units i out(powerpath) v out current available before loading bat 1x mode, bat = 3.3v 5x mode, bat = 3.3v 10x mode, bat = 3.3v suspend mode 135 672 1251 0.32 ma ma ma ma v clprog clprog servo voltage in current limit 1x, 5x, 10x modes suspend mode 1.188 100 v mv v uvlo_vbus v bus undervoltage lockout rising threshold falling threshold 3.95 4.30 4.00 4.35 v v v uvlo_vbus-bat v bus to bat differential undervoltage lockout rising threshold falling threshold 200 50 mv mv v out v out voltage 1x, 5x, 10x modes, 0v < bat < 4.2v, i out = 0ma, battery charger off 3.4 bat + 0.3 4.7 v usb suspend mode, i out = 250a 4.5 4.6 4.7 v f osc switching frequency l 1.8 2.25 2.7 mhz r pmos_powerpath pmos on-resistance 0.18 r nmos_powerpath nmos on-resistance 0.30 i peak_powerpath peak switch current limit 1x, 5x modes 10x mode 2 3 a a battery charger v float bat regulated output voltage l 4.179 4.165 4.200 4.200 4.221 4.235 v v i chg constant current mode charge current r prog = 5k 980 185 1022 204 1065 223 ma ma i bat battery drain current v bus > v uvlo , battery charger off, i out = 0a v bus = 0v, i out = 0a (ideal diode mode) 2 3.5 27 5 38 a a v prog prog pin servo voltage 1.000 v v prog_trkl prog pin servo voltage in trickle charge bat < v trkl 0.100 v v c/10 c/10 threshold voltage at prog 100 mv h prog ratio of i bat to prog pin current 1022 ma/ma i trkl trickle charge current bat < v trkl 100 ma v trkl trickle charge threshold voltage bat rising 2.7 2.85 3.0 v v trkl trickle charge hysteresis voltage 135 mv v rechrg recharge battery threshold voltage threshold voltage relative to v float C75 C100 C125 mv t term safety timer termination timer starts when bat = v float 3.3 4 5 hour t badbat bad battery termination time bat < v trkl 0.42 0.5 0.63 hour h c/10 end of charge indication current ratio (note 5) 0.088 0.1 0.112 ma/ma v chrg chrg pin output low voltage i chrg = 5ma 65 100 mv i chrg chrg pin leakage current v chrg = 5v 1 a r on_chg battery charger power fet on-resistance (between v out and bat) 0.18 t lim junction temperature in constant temperature mode 110 c electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v bus = 5v, v in1 = v in2 = v in3 = v out3 = 3.8v, bat = 3.8v, dv cc = 3.3v, r prog = 1k, r clprog = 3.01k, unless otherwise noted.
LTC3556 4 3556p electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v bus = 5v, v in1 = v in2 = v in3 = v out3 = 3.8v, bat = 3.8v, dv cc = 3.3v, r prog = 1k, r clprog = 3.01k, unless otherwise noted. symbol parameter conditions min typ max units ntc v cold cold temperature fault threshold voltage rising threshold hysteresis 75.0 76.5 1.5 78.0 %v bus %v bus v hot hot temperature fault threshold voltage falling threshold hysteresis 33.4 34.9 1.5 36.4 %v bus %v bus v dis ntc disable threshold voltage falling threshold hysteresis 0.7 1.7 50 2.7 %v bus mv i ntc ntc leakage current v ntc = v bus = 5v C50 50 na ideal diode v fwd forward voltage v bus = 0v, i out = 10ma i out = 10ma 2 15 mv mv r dropout internal diode on-resistance, dropout v bus = 0v 0.18 i max_diode internal diode current limit 1.6 a always on 3.3v supply v ldo3v3 regulated output voltage 0ma < i ldo3v3 < 25ma 3.1 3.3 3.5 v r cl_ldo3v3 closed-loop output resistance 4 r ol_ldo3v3 dropout output resistance 23 logic (enall, pgoodall) v il logic low input voltage enall pin 0.4 v v ih logic high input voltage enall pin 1.2 v r pd pull-down resistance enall pin 4.5 m v ol logic low output voltage pgoodall pin, i pull-up = 5ma 0.07 0.2 v i oh logic high leakage current pgoodall pin, v pgoodall = 5v 1 a t pgoodall pgoodall assertion delay 230 ms i 2 c port (note 9) dv cc input supply voltage 1.6 5.5 v i dvcc dv cc current scl/sda = 0khz 0.3 1 a v dvcc_uvlo dv cc uvlo 1.0 v address i 2 c address 0001 001[0] v ih sda, scl v il sda, scl input high voltage input low voltage 70 30 %dv cc %dv cc i ih , i il sda, scl input high/low current C1 0 1 a v ol sda sda output low voltage i sda = 3ma 0.4 v f scl clock operating frequency 400 khz t buf bus free time between stop and start condition 1.3 s t hd_sta hold time after (repeated) start condition 0.6 s t su_sta repeated start condition setup time 0.6 s t su_sto stop condition setup time 0.6 s t hd_dat(o) data hold time output 0 900 ns
LTC3556 5 3556p electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v bus = 5v, v in1 = v in2 = v in3 = v out3 = 3.8v, bat = 3.8v, dv cc = 3.3v, r prog = 1k, r clprog = 3.01k, unless otherwise noted. symbol parameter conditions min typ max units t hd_dat(i) data hold time input 0 ns t su_dat data setup time 100 ns t low scl clock low period 1.3 s t high scl clock high period 0.6 s t f clock/data fall time c b = capacitance of one bus line (pf) 20 + 0.1c b 300 ns t r clock/data rise time c b = capacitance of one bus line (pf) 20 + 0.1c b 300 ns t sp input spike suppression pulse width 50 ns switching regulators 1, 2 and 3 v in1,2,3 input supply voltage 2.7 5.5 v v outuvlo v out uvlov out falling v out uvlov out rising v in1,2,3 connected to v out through low impedance. switching regulators are disabled in uvlo 2.5 2.6 2.8 2.9 v v f osc oscillator frequency l 1.8 2.25 2.7 mhz switching regulator 1 (buck) i vin1 pulse skip mode input current burst mode ? input current forced burst mode input current ldo mode input current shutdown input current i out1 = 0a (note 6) i out1 = 0a (note 6) i out1 = 0a (note 6) i out1 = 0a (note 6) i out1 = 0a, fb1 = 0v 225 35 20 20 400 60 35 35 1 a a a a a i lim1 pmos switch current limit pulse skip/burst mode operation 600 800 1100 ma i out1 available output current pulse skip/burst mode operation (note 9) forced burst mode operation (note 9) ldo mode (note 9) 400 60 50 ma ma ma v fbhigh1 maximum servo voltage full scale (1, 1, 1, 1) (note 7) l 0.780 0.800 0.820 v v fblow1 minimum servo voltage zero scale (0, 0, 0, 0) (note 7) l 0.405 0.425 0.445 v v lsb1 v fb1 servo voltage step size 25 mv r p1 pmos r ds(on) 0.6 r n1 nmos r ds(on) 0.7 r ldo_cl1 ldo mode closed-loop r out 0.25 r ldo_ol1 ldo mode open-loop r out (note 8) 2.5 i fb1 fb1 input current v fb1 = 0.85v C50 50 na d1 maximum duty cycle l 100 % r sw1 sw1 pull-down in shutdown 10 k switching regulator 2 (buck) i vin2 pulse skip mode input current burst mode input current forced burst mode input current ldo mode input current shutdown input current i out2 = 0a (note 6) i out2 = 0a (note 6) i out2 = 0a (note 6) i out2 = 0a (note 6) i out2 = 0a, fb2 = 0v 225 35 20 20 400 60 35 35 1 a a a a a i lim2 pmos switch current limit pulse skip/burst mode operation 600 800 1100 ma i out2 available output current pulse skip/burst mode operation (note 9) forced burst mode operation (note 9) ldo mode (note 9) 400 60 50 ma ma ma burst mode is a registered trademark of linear technology corporation.
LTC3556 6 3556p electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v bus = 5v, v in1 = v in2 = v in3 = v out3 = 3.8v, bat = 3.8v, dv cc = 3.3v, r prog = 1k, r clprog = 3.01k, unless otherwise noted. symbol parameter conditions min typ max units v fb2 v fb2 servo voltage (note 7) l 0.780 0.800 0.820 v r p2 pmos r ds(on) 0.6 r n2 nmos r ds(on) 0.7 r ldo_cl2 ldo mode closed-loop r out 0.25 r ldo_ol2 ldo mode open-loop r out (note 8) 2.5 i fb2 fb2 input current v fb2 = 0.85v C50 50 na d2 maximum duty cycle l 100 % r sw2 sw2 pull-down in shutdown 10 k switching regulator 3 (buck-boost) i vin3 input current pwm mode, i out3 = 0a burst mode operation, i out3 = 0a shutdown 220 13 0 400 20 1 a a a v out3(low) minimum regulated output voltage for burst mode operation or synchronous pwm operation 2.65 2.75 v v out3(high) maximum regulated output voltage 5.50 5.60 v i limf3 forward current limit (switch a) pwm mode l 2 2.5 3 a i peak3(burst) forward burst current limit (switch a) burst mode operation l 200 275 350 ma i zero3(burst) reverse burst current limit (switch d) burst mode operation l C30 0 30 ma i max3(burst) maximum deliverable output current in burst mode operation 2.7v v in3 5.5v, 2.75v v out3 5.5v (note 9) 50 ma v fbhigh3 maximum servo voltage full scale (1, 1, 1, 1) l 0.780 0.800 0.820 v v fblow3 minimum servo voltage zero scale (0, 0, 0, 0) l 0.405 0.425 0.445 v v lsb3 v fb3 servo voltage step size 25 mv i fb3 fb3 input current v fb3 = 0.8v C50 50 na r ds(on)p pmos r ds(on) switches a, d 0.22 r ds(on)n nmos r ds(on) switches b, c 0.17 i leak(p) pmos switch leakage switches a, d C1 1 a i leak(n) nmos switch leakage switches b, c C1 1 a r vout3 v out3 pull-down in shutdown 10 k d buck(max) maximum buck duty cycle pwm mode l 100 % d boost(max) maximum boost duty cycle pwm mode 75 % t ss3 soft-start time 0.5 ms note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTC3556e is guaranteed to meet performance speci?cations from 0c to 85c. speci?cations over the C40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: the LTC3556e includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the speci?ed maximum operating junction temperature may impair device reliability. note 4: total input current is the sum of quiescent current, i vbusq , and measured current given by: v clprog /r clprog ? (h clprog +1) note 5: h c/10 is expressed as a fraction of measured full charge current with indicated prog resistor. note 6: fbx above regulation such that regulator is in sleep. speci? cation does not include resistive divider current re? ected back to v inx . note 7: applies to pulse skip, burst mode operation and forced burst mode operation only. note 8: inductor series resistance adds to open-loop r out . note 9: guaranteed by design.
LTC3556 7 3556p typical performance characteristics ideal diode v-i characteristics ideal diode resistance vs battery voltage output voltage vs load current (battery charger disabled) usb limited battery charge current vs battery voltage usb limited battery charge current vs battery voltage battery drain current vs battery voltage powerpath switching regulator ef? ciency vs load current battery charging ef? ciency vs battery voltage with no external load (p bat /p bus ) v bus current vs v bus voltage (suspend) forward voltage (v) 0 current (a) 0.6 0.8 1.0 0.16 3556 g01 0.4 0.2 0 0.04 0.08 0.12 0.20 internal ideal diode with supplemental external vishay si2333 pmos internal ideal diode only v bus = 0v v bus = 5v battery voltage (v) 2.7 resistance () 0.15 0.20 0.25 3.9 3556 g02 0.10 0.05 0 3.0 3.3 3.6 4.2 internal ideal diode with supplemental external vishay si2333 pmos internal ideal diode load current (ma) 0 output voltage (v) 4.00 4.25 4.50 800 3556 g03 3.75 3.50 3.25 200 400 600 1000 bat = 4v bat = 3.4v v bus = 5v 5x mode battery voltage (v) 2.7 500 600 700 3.9 3556 g04 400 300 3.0 3.3 3.6 4.2 200 100 0 charge current (ma) v bus = 5v r prog = 1k r clprog = 3.01k 5x usb setting, battery charger set for 1a battery voltage (v) 2.7 0 charge current (ma) 25 50 75 100 125 150 3.0 3.3 3.6 3.9 3556 g05 4.2 v bus = 5v r prog = 1k r clprog = 3.01k 1x usb setting, battery charger set for 1a battery voltage (v) 2.7 battery current (a) 15 20 25 3.9 3556 g06 10 5 0 3.0 3.3 3.6 4.2 v bus = 0v v bus = 5v (suspend mode) i vout = 0a load current (a) 0.01 40 efficiency (%) 50 60 70 80 100 0.1 1 3556 g07 90 5x, 10x mode 1x mode bat = 3.8v battery voltage (v) 2.7 efficiency (%) 90 100 3.9 3556 g08 80 70 60 3.0 3.3 3.6 4.2 r clprog = 3.01k r prog = 1k i vout = 0ma 5x charging efficiency 1x charging efficiency bus voltage (v) 0 quiescent current (a) 30 40 50 4 3556 g09 20 10 0 1 2 3 5 bat = 3.8v i vout = 0ma
LTC3556 8 3556p typical performance characteristics output voltage vs load current in suspend v bus current vs load current in suspend 3.3v ldo output voltage vs load current, v bus = 0v battery charge current vs temperature battery charger float voltage vs temperature low-battery (instant on) output voltage vs temperature oscillator frequency vs temperature v bus quiescent current vs temperature v bus quiescent current in suspend vs temperature load current (ma) 0 output voltage (v) 4.0 4.5 5.0 0.4 3556 g10 3.5 3.0 2.5 0.1 0.2 0.3 0.5 v bus = 5v bat = 3.3v r clprog = 3k load current (ma) 0 v bus current (ma) 0.3 0.4 0.5 0.4 3556 g11 0.2 0.1 0 0.1 0.2 0.3 0.5 v bus = 5v bat = 3.3v r clprog = 3.01k load current (ma) 0 output voltage (v) 3.0 3.2 20 3556 g12 2.8 2.6 5 10 15 25 3.4 bat = 3v bat = 3.1v bat = 3.2v bat = 3.3v bat = 3.6v bat = 3.5v bat = 3.4v bat = 3.9v, 4.2v temperature (c) C40 0 charge current (ma) 100 200 300 400 040 80 120 3556 g13 500 600 C20 20 60 100 thermal regulation r prog = 2k 10x mode temperature (c) C40 float voltage (v) 4.19 4.20 60 3556 g14 4.18 4.17 C15 10 35 85 4.21 temperature (c) C40 output voltage (v) 3.64 3.66 60 3556 g15 3.62 3.60 C15 10 35 85 3.68 bat = 2.7v i vout = 100ma 5x mode temperature (c) C40 frequency (mhz) 2.2 2.4 60 3556 g16 2.0 1.8 C15 10 35 85 2.6 v bus = 5v bat = 3.6v v bus = 0v bat = 3v v bus = 0v bat = 2.7v v bus = 0v temperature (c) C40 quiescent current (ma) 9 12 60 3556 g17 6 3 C15 10 35 85 15 v bus = 5v i vout = 0a 5x mode 1x mode temperature (c) C40 quiescent current (a) 50 60 60 3556 g18 40 30 C15 10 35 85 70 i vout = 0a
LTC3556 9 3556p typical performance characteristics pgoodall, chrg pin current vs voltage (pull-down state) 3.3v ldo step response (5ma to 15ma) battery drain current vs temperature switching regulators 1, 2 pulse skip mode quiescent currents pgoodall, chrg pin voltage (v) 0 pgoodall, chrg pin current (ma) 60 80 100 4 3556 g19 40 20 0 1 2 3 5 v bus = 5v bat = 3.8v i ldo3v3 5ma/div 0ma 20s/div bat = 3.8v 3556 g20 v ldo3v3 20mv/div ac coupled temperature (c) C40 battery current (a) 30 40 50 60 3556 g21 20 10 0 C15 10 35 85 bat = 3.8v v bus = 0v all regulators off temperature (c) C40 input current (a) input current (ma) 275 300 325 60 3556 g22 250 225 200 1.85 1.90 1.95 1.80 1.75 1.70 C15 10 35 85 v out1,2 = 2.5v (constant frequency) v out1,2 = 1.25v (pulse skipping) v in1,2 = 3.8v switching regulators 1, 2 pulse skip mode ef? ciency switching regulators 1, 2 burst mode ef? ciency switching regulators 1, 2 forced burst mode ef? ciency load current (ma) 1 40 efficiency (%) 50 60 70 80 10 100 1000 3556 g23 30 20 10 0 90 100 v out1,2 = 2.5v v out1,2 = 1.2v v out1,2 = 1.8v v in1,2 = 3.8v load current (ma) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.1 10 100 1000 3556 g24 0 1 v out1,2 = 2.5v v out1,2 = 1.2v v out1,2 = 1.8v v in1,2 = 3.8v load current (ma) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.1 10 100 1000 3556 g25 0 1 v out1,2 = 2.5v v out1,2 = 1.2v v out1,2 = 1.8v v in1,2 = 3.8v switching regulators 1, 2 load regulation at v out1,2 = 1.2v switching regulators 1, 2 load regulation at v out1,2 = 1.8v load current (ma) 1.185 output voltage (v) 1.200 1.215 1.230 0.1 10 100 1000 3556 g26 1.170 1 v bus = 3.8v burst mode operation forced burst mode operation pulse skip mode load current (ma) 1.778 output voltage (v) 1.800 1.823 1.845 0.1 10 100 1000 3556 g27 1.755 1 v bus = 3.8v burst mode operation forced burst mode operation pulse skip mode
LTC3556 10 3556p typical performance characteristics r ds(on) s for switching regulator 3 vs temperature switching regulator 3 ef? ciency vs load current switching regulator 3 pwm mode ef? ciency vs input voltage switching regulators 1, 2 load regulation at v out1,2 = 2.5v load current (ma) 2.47 output voltage (v) 2.50 2.53 2.56 0.1 10 100 1000 3556 g28 2.44 1 v bus = 3.8v burst mode operation forced burst mode operation pulse skip mode switching regulator 3 reduction in current deliverability at low v in3 v in3 (v) 2.7 0 reduction below 1a (ma) 50 100 150 200 300 3.1 3.5 3.9 4.3 3556 g34 4.7 250 start-up with a current source load steady state load v out3 = 3.3v t a = 27c start-up with a resistive load switching regulator 3 burst mode operation input quiescent current temperature (c) C55 i vin3 (a) 13.0 13.5 12.5 12.0 C15 5 45 C35 25 65 105 85 125 11.5 11.0 14.0 3556 g29 v out3 = 3.3v t a = 27c v in3 = 3v v in3 = 4.5v v in3 = 3.6v v in3 = v out3 = 3v temperature (c) C55 pmos r ds(on) () 0.20 0.25 0.15 0.10 C15 5 45 C35 25 65 105 85 125 0.05 0 0.30 nmos r ds(on) () 0.30 0.35 0.25 0.20 0.15 0.10 0.40 3556 g31 pmos nmos v in3 = v out3 = 4.5v v in3 = v out3 = 3.6v v in3 = 4.5v v in3 = 3v v in3 = 3.6v temperature (c) C55 i limf3 (ma) 2500 2550 2450 2400 C15 5 45 C35 25 65 105 85 125 2350 2300 2600 3556 g30 v in3 = 3v v in3 = 4.5v v in3 = 3.6v switching regulator 3 forward current limit vs temperature load current (ma) efficiency (%) 0.1 10 100 1000 1 3556 g32 v out3 = 3.3v t a = 27c v in3 = 3v v in3 = 3.6v v in3 = 4.5v burst mode operation curves pwm mode curves 40 50 60 70 80 30 20 10 0 90 100 40 50 60 70 80 30 20 10 0 90 100 v in3 (v) 2.7 efficiency (%) 3.1 3.5 3.9 4.3 3556 g33 4.7 v out3 = 3.3v t a = 27c i out3 = 200ma i out3 = 50ma i out3 = 1000ma
LTC3556 11 3556p pin functions ldo3v3 (pin 1): 3.3v ldo output pin. this pin provides a regulated, always-on, 3.3v supply voltage. ldo3v3 gets its power from v out . it may be used for light loads such as a watchdog microprocessor or real time clock. a 1f capacitor is required from ldo3v3 to ground. if the ldo3v3 output is not used it should be disabled by connecting it to v out . clprog (pin 2): usb current limit program and moni- tor pin. a resistor from clprog to ground determines the upper limit of the current drawn from the v bus pin. a fraction of the v bus current is sent to the clprog pin when the synchronous switch of the powerpath switching regulator is on. the switching regulator delivers power until the clprog pin reaches 1.188v. several v bus current limit settings are available via user input which will typically correspond to the 500ma and 100ma usb speci?cations. a multilayer ceramic averaging capacitor or r-c network is required at clprog for ?ltering. ntc (pin 3): input to the thermistor monitoring circuits. the ntc pin connects to a batterys thermistor to deter- mine if the battery is too hot or too cold to charge. if the batterys temperature is out of range, charging is paused until it re-enters the valid range. a low drift bias resistor is required from v bus to ntc and a thermistor is required from ntc to ground. if the ntc function is not desired, the ntc pin should be grounded. sw1 (pin 4): power transmission pin for (buck) switch- ing regulator 1. v in1 (pin 5): power input for (buck) switching regula- tor 1. this pin will generally be connected to v out . a 1f mlcc capacitor is recommended on this pin. fb1 (pin 6): feedback input for (buck) switching regula- tor 1. when regulator 1s control loop is complete, this pin servos to 1 of 16 possible set-points based on the commanded value from the i 2 c serial port. see table 4. fb3 (pin 7): feedback input for (buck-boost) switching regulator 3. when regulator 3s control loop is complete, this pin servos to 1 of 16 possible set-points based on the commanded value from the i 2 c serial port. see table 4. v c3 (pin 8): output of the error ampli? er and voltage compensation node for (buck-boost) switching regula- tor 3. external type i or type iii compensation (to fb3) connects to this pin. see applications information section for selecting buck-boost compensation components. swab3 (pin 9): switch node for (buck-boost) switching regulator 3. connected to internal power switches a and b. external inductor connects between this node and swcd3. dv cc (pin 10): logic supply for the i 2 c serial port. v in3 (pin 11): power input for (buck-boost) switching regulator 3. this pin will generally be connected to v out . a 1f (min) mlcc capacitor is recommended on this pin. v out3 (pin 12): regulated output voltage for (buck-boost) switching regulator 3. switching regulator 3 step response (0ma to 300ma) start-up sequencing with seq = 0v v in1 = v in2 = v in3 = 4.2v all outputs loaded with 5ma 100s/div v out3 100mv/div ac coupled 300ma 0 i out3 200ma/ div 3556 g35 v in3 = 3.8v v out3 = 3.3v 200s/div v out3 = 3.3v enall v out2 = 1.8v v out1 = 1.6v 1v/div 3556 g36 typical performance characteristics
LTC3556 12 3556p pin functions scl (pin 13): clock input pin for the i 2 c serial port. the i 2 c logic levels are scaled with respect to dv cc . swcd3 (pin 14): switch node for (buck-boost) switch- ing regulator 3. connected to internal power switches c and d. external inductor connects between this node and swab3. pgoodall (pin 15): logic output. this in an open-drain output which indicates that all enabled switching regula- tors have settled to their ?nal value. it can be used as a power-on reset for the primary microprocessor. sda (pin 16): data input pin for the i 2 c serial port. the i 2 c logic levels are scaled with respect to dv cc . fb2 (pin 17): feedback input for (buck) switching regu- lator 2. when regulator 2s control loop is complete, this pin servos to a ? xed voltage of 0.8v. v in2 (pin 18): power input for (buck) switching regula- tor 2. this pin will generally be connected to v out . a 1f mlcc capacitor is recommended on this pin. sw2 (pin 19): power transmission pin for (buck) switch- ing regulator 2. prog (pin 20): charge current program and charge current monitor pin. connecting a resistor from prog to ground programs the charge current. if suf?cient in- put power is available in constant-current mode, this pin servos to 1v. the voltage on this pin always represents the actual charge current. chrg (pin 21): open-drain charge status output. the chrg pin indicates the status of the battery charger. four possible states are represented by chrg : charging, not charging, unresponsive battery and battery temperature out of range. chrg is modulated at 35khz and switches between a low and a high duty cycle for easy recogni- tion by either humans or microprocessors. see table 1. chrg requires a pull-up resistor and/or led to provide indication. gate (pin 22): analog output. this pin controls the gate of an optional external p-channel mosfet transistor used to supplement the ideal diode between v out and bat. the external ideal diode operates in parallel with the internal ideal diode. the source of the p-channel mosfet should be connected to v out and the drain should be connected to bat. if the external ideal diode fet is not used, gate should be left ?oating. bat (pin 23): single cell li-ion battery pin. depending on available v bus power, a li-ion battery on bat will either deliver power to v out through the ideal diode or be charged from v out via the battery charger. v out (pin 24): output voltage of the switching power- path controller and input voltage of the battery charger. the majority of the portable product should be powered from v out . the LTC3556 will partition the available power between the external load on v out and the internal battery charger. priority is given to the external load and any extra power is used to charge the battery. an ideal diode from bat to v out ensures that v out is powered even if the load exceeds the allotted power from v bus or if the v bus power source is removed. v out should be bypassed with a low impedance ceramic capacitor. v bus (pin 25): primary input power pin. this pin delivers power to v out via the sw pin by drawing controlled current from a dc source such as a usb port or wall adapter. sw (pin 26): power transmission pin for the usb power path. the sw pin delivers power from v bus to v out via the step-down switching regulator. a 3.3h inductor should be connected from sw to v out . seq (pin 27): sequence select logic input. three-state input which determines start-up sequence after enall is asserted. if tied to gnd, start-up sequence is: buck 1 buck 2 buck-boost if tied to v out , start-up sequence is: buck 1 buck-boost buck 2 if left ? oating, start-up sequence is: buck-boost buck 1 buck 2 enall (pin 28): enable all logic input. enables all three switching regulators in sequence according to the state of the seq pin. active high. has a 5.5m internal pull-down resistor. alternately, all switching regulators can be indi- vidually enabled via the i 2 c serial port. exposed pad (pin 29): ground. the exposed pad should be connected to a continuous ground plane on the second layer of the printed circuit board by several vias directly under the LTC3556.
LTC3556 13 3556p block diagram 11 12 29 + + C + C v in3 a b d c swab3 v out3 gnd 3556 bd 21 chrg 2 clprog 3 ntc 28 enall 10 dv cc 27 seq 16 sda 13 scl 1a 2.25mhz (buck-boost) switching regulator 3 9 swcd3 14 18 17 v in2 sw2 fb2 400ma 2.25mhz (buck) switching regulator 2 19 5 6 v in1 20 prog 23 bat 15mv 0.3v 3.6v en1 en2 en3 ideal 1.188v sw1 fb1 8 v c3 400ma 2.25mhz (buck) switching regulator 1 2.25mhz powerpath switching regulator 4 d/a d/a 4 4 i 2 c port master logic and sequencer cc/cv charger 3.3v ldo charge status 15 pgoodall power good 22 gate 24 v out sw + C + C + C battery temperature monitor suspend ldo 500a 26 ldo3v3 1 25 v bus 7 fb3
LTC3556 14 3556p operation timing diagram t su, dat t hd, sta t hd, dat sda scl t su, sta t hd, sta t su, sto 3556 td t buf t low t high start condition repeated start condition stop condition start condition t r t f t sp ack ack 123 address wr 456789123456789123456789 00 01 0 01 0 00010010 a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 ack stop start sda scl data byte a data byte b i 2 c timing diagram introduction the LTC3556 is a highly integrated power management ic which includes a high ef?ciency switch mode powerpath controller, a battery charger, an ideal diode, an always-on ldo, two 400ma buck switching regulators and a 1a buck- boost switching regulator. the entire chip is controllable via an i 2 c serial port. designed speci?cally for usb applications, the powerpath controller incorporates a precision average input current step-down switching regulator to make maximum use of the allowable usb power. because power is conserved, the LTC3556 allows the load current on v out to exceed the current drawn by the usb port without exceeding the usb load speci?cations. the powerpath switching regulator and battery charger communicate to ensure that the input current never violates the usb speci?cations. the ideal diode from bat to v out guarantees that ample power is always available to v out even if there is insuf- ?cient or absent power at v bus . an always-on ldo provides a regulated 3.3v from avail- able power at v out . drawing very little quiescent current, this ldo will be on at all times and can be used to supply up to 25ma. the three switching regulators can be enabled together in any desired sequence via the enall and seq pins or can be independently enabled via the i 2 c serial port. under i 2 c control, one of the 400ma bucks and the 1a buck-boost have adjustable set-points so that voltages can be reduced when high processor performance is not needed. along with constant frequency pwm mode, all three switching regulators have a low power burst-only mode setting for signi?cantly reduced quiescent current under light load conditions. additionally, the 400ma bucks can be con? gured for automatic burst mode operation or ldo mode. high ef?ciency switching powerpath controller whenever v bus is available and the powerpath switch- ing regulator is enabled, power is delivered from v bus to v out via sw. v out drives the combination of the external load (including switching regulators 1, 2 and 3) and the battery charger. if the combined load does not exceed the powerpath switching regulators programmed input current limit, v out will track 0.3v above the battery (bat-track). by keeping the voltage across the battery charger low, ef?ciency is optimized because power lost to the linear battery charger is minimized. power available to the external load is therefore optimized.
LTC3556 15 3556p operation if the combined load at v out is large enough to cause the switching power supply to reach the programmed input current limit, the battery charger will reduce its charge cur- rent by that amount necessary to enable the external load to be satis?ed. even if the battery charge current is set to exceed the allowable usb current, the usb speci?cation will not be violated. the switching regulator will limit the average input current so that the usb speci?cation is never violated. furthermore, load current at v out will always be prioritized and only remaining available power will be used to charge the battery. if the voltage at bat is below 3.3v, or the battery is not present and the load requirement does not cause the switching regulator to exceed the usb speci?cation, v out will regulate at 3.6v, thereby providing instant-on operation. if the load exceeds the available power, v out will drop to a voltage between 3.6v and the battery voltage. if there is no battery present when the load exceeds the available usb power, v out can drop toward ground. the power delivered from v bus to v out is controlled by a 2.25mhz constant-frequency step-down switching regulator. to meet the usb maximum load speci?cation, the switching regulator includes a control loop which ensures that the average input current is below the level programmed at clprog. the current at clprog is a fraction (h clprog C1 ) of the v bus current. when a programming resistor and an averaging capacitor are connected from clprog to gnd, the voltage on clprog represents the average input current of the switching regulator. when the input current approaches the programmed limit, clprog reaches v clprog , 1.188v and power out is held constant. the input current limit is programmed by the b1 and b0 bits of the i 2 c serial port. it can be con?gured to limit average input current to one of several possible settings as well as be deactivated (usb suspend). the input current limit will be set by the v clprog servo voltage and the resistor on clprog according to the following expression: ii v r h vbus vbusq clprog clprog clprog =+ + () ?1 figure 1 shows the range of possible voltages at v out as a function of battery voltage. bat (v) 2.4 4.5 4.2 3.9 3.6 3.3 3.0 2.7 2.4 3.3 3.9 3556 f01 2.7 3.0 3.6 4.2 v out (v) no load 300mv figure 1. v out vs bat ideal diode from bat to v out the LTC3556 has an internal ideal diode as well as a con- troller for an optional external ideal diode. the ideal diode controller is always on and will respond quickly whenever v out drops below bat. if the load current increases beyond the power allowed from the switching regulator, additional power will be pulled from the battery via the ideal diode. furthermore, if power to v bus (usb or wall power) is removed, then all of the application power will be provided by the battery via the ideal diode. the transition from input power to battery power at v out will be quick enough to allow only the 10f capacitor to keep v out from drooping. the ideal diode consists of a precision ampli?er that enables a large on- chip p-channel mosfet transistor whenever the voltage at forward voltage (mv) (bat C v out ) 0 current (ma) 600 1800 2000 2200 120 240 300 3556 f02 200 1400 1000 400 1600 0 1200 800 60 180 360 480 420 vishay si2333 optional external ideal diode LTC3556 ideal diode on semiconductor mbrm120lt3 figure 2. ideal diode operation
LTC3556 16 3556p operation v out is approximately 15mv (v fwd ) below the voltage at bat. the resistance of the internal ideal diode is approxi- mately 180m. if this is suf?cient for the application, then no external components are necessary. however, if more conductance is needed, an external p-channel mosfet transistor can be added from bat to v out . when an external p-channel mosfet transistor is present, the gate pin of the LTC3556 drives its gate for automatic ideal diode control. the source of the external p-chan- nel mosfet should be connected to v out and the drain should be connected to bat. capable of driving a 1nf load, the gate pin can control an external p-channel mosfet transistor having an on-resistance of 40m or lower. suspend ldo if the LTC3556 is con?gured for usb suspend mode, the switching regulator is disabled and the suspend ldo provides power to the v out pin (presuming there is power available to v bus ). this ldo will prevent the battery from running down when the portable product has access to a suspended usb port. regulating at 4.6v, this ldo only becomes active when the switching converter is disabled (suspended). to remain compliant with the usb speci?ca- tion, the input to the ldo is current limited so that it will not exceed the 500a low power suspend speci?cation. if the load on v out exceeds the suspend current limit, the additional current will come from the battery via the ideal diode. 3.3v always-on supply the LTC3556 includes a low quiescent current low dropout regulator that is always powered. this ldo can be used to provide power to a system pushbutton controller, standby microcontroller or real time clock. designed to deliver up to 25ma, the always-on ldo requires at least a 1f low impedance ceramic bypass capacitor for compensation. the ldo is powered from v out , and therefore will enter dropout at loads less than 25ma as v out falls near 3.3v. if the ldo3v3 output is not used, it should be disabled by connecting it to v out . v bus undervoltage lockout (uvlo) an internal undervoltage lockout circuit monitors v bus and keeps the powerpath switching regulator off until v bus rises above 4.30v and is about 200mv above the battery voltage. hysteresis on the uvlo turns off the regulator if v bus drops below 4.00v or to within 50mv of bat. when this happens, system power at v out will be drawn from the battery via the ideal diode. + C + + C 0.3v 1.188v 3.6v clprog i switch / h clprog + C + C 15mv ideal diode pwm and gate drive average input current limit controller average output voltage limit controller constant current constant voltage battery charger + C 2 gate 22 v out 24 sw 3.5v to (bat + 0.3v) to system load optional external ideal diode pmos single cell li-ion 3556 f03 26 bat 23 v bus to usb or wall adapter 25 + figure 3. powerpath block diagram
LTC3556 17 3556p operation battery charger the LTC3556 includes a constant-current/constant-volt- age battery charger with automatic recharge, automatic termination by safety timer, low voltage trickle charging, bad cell detection and thermistor sensor input for out-of- temperature charge pausing. battery preconditioning when a battery charge cycle begins, the battery charger ?rst determines if the battery is deeply discharged. if the battery voltage is below v trkl , typically 2.85v, an automatic trickle charge feature sets the battery charge current to 10% of the programmed value. if the low voltage persists for more than 1/2 hour, the battery charger automatically terminates and indicates via the chrg pin that the battery was unresponsive. once the battery voltage is above 2.85v, the battery charger begins charging in full power constant-current mode. the current delivered to the battery will try to reach 1022v/ r prog . depending on available input power and external load conditions, the battery charger may or may not be able to charge at the full programmed rate. the external load will always be prioritized over the battery charge current. the usb current limit programming will always be observed and only additional power will be available to charge the battery. when system loads are light, battery charge current will be maximized. charge termination the battery charger has a built-in safety timer. when the voltage on the battery reaches the pre-programmed ?oat voltage of 4.200v, the battery charger will regulate the battery voltage and the charge current will decrease naturally. once the battery charger detects that the battery has reached 4.200v, the four hour safety timer is started. after the safety timer expires, charging of the battery will discontinue and no more current will be delivered. automatic recharge after the battery charger terminates, it will remain off drawing only microamperes of current from the battery. if the portable product remains in this state long enough, the battery will eventually self discharge. to ensure that the battery is always topped off, a charge cycle will auto- matically begin when the battery voltage falls below 4.1v. in the event that the safety timer is running when the battery voltage falls below 4.1v, it will reset back to zero. to prevent brief excursions below 4.1v from resetting the safety timer, the battery voltage must be below 4.1v for more than 1.3ms. the charge cycle and safety timer will also restart if the v bus uvlo cycles low and then high (e.g., v bus is removed and then replaced), or if the battery charger is cycled on and off by the i 2 c port. charge current the charge current is programmed using a single resis- tor from prog to ground. 1/1022th of the battery charge current is sent to prog which will attempt to servo to 1.000v. thus, the battery charge current will try to reach 1022 times the current in the prog pin. the program resistor and the charge current are calculated using the following equations: r v i i v r prog chrg chrg prog == 1022 1022 , in either the constant-current or constant-voltage charging modes, the voltage at the prog pin will be proportional to the actual charge current delivered to the battery. there- fore, the actual charge current can be determined at any time by monitoring the prog pin voltage and using the following equation: i v r bat prog prog = ? 1022 in many cases, the actual battery charge current, i bat , will be lower than i chrg due to limited input power available and prioritization with the system load drawn from v out . charge status indication the chrg pin indicates the status of the battery charger. four possible states are represented by chrg which in- clude charging, not charging, unresponsive battery, and battery temperature out of range. the signal at the chrg pin can be easily recognized as one of the above four states by either a human or a mi- croprocessor. an open-drain output, the chrg pin can
LTC3556 18 3556p drive an indicator led through a current limiting resistor for human interfacing or simply a pull-up resistor for microprocessor interfacing. to make the chrg pin easily recognized by both humans and microprocessors, the pin is either low for charging, high for not charging, or it is switched at high frequency (35khz) to indicate the two possible faults, unresponsive battery and battery temperature out of range. when charging begins, chrg is pulled low and remains low for the duration of a normal charge cycle. when charg- ing is complete, i.e., the bat pin reaches 4.200v and the charge current has dropped to one tenth of the programmed value, the chrg pin is released (hi-z). if a fault occurs, the pin is switched at 35khz. while switching, its duty cycle is modulated between a high and low value at a very low frequency. the low and high duty cycles are disparate enough to make an led appear to be on or off thus giving the appearance of blinking. each of the two faults has its own unique blink rate for human recognition as well as two unique duty cycles for machine recognition. the chrg pin does not respond to the c/10 threshold if the LTC3556 is in v bus current limit. this prevents false end of charge indications due to insuf?cient power avail- able to the battery charger. table 1 illustrates the four possible states of the chrg pin when the battery charger is active. table 1. chrg signal status frequency modulation (blink) frequency duty cycles charging 0hz 0hz (lo-z) 100% not charging 0hz 0hz (hi-z) 0% ntc fault 35khz 1.5hz at 50% 6.25% to 93.75% bad battery 35khz 6.1hz at 50% 12.5% to 87.5% an ntc fault is represented by a 35khz pulse train whose duty cycle alternates between 6.25% and 93.75% at a 1.5hz rate. a human will easily recognize the 1.5hz rate as a slow blinking which indicates the out-of-range battery temperature while a microprocessor will be able to decode either the 6.25% or 93.75% duty cycles as an ntc fault. if a battery is found to be unresponsive to charging (i.e., its voltage remains below 2.85v for 1/2 hour), the chrg pin gives the battery fault indication. for this fault, a human would easily recognize the frantic 6.1hz fast blink of the led while a microprocessor would be able to decode either the 12.5% or 87.5% duty cycles as a bad battery fault. note that the LTC3556 is a 3-terminal powerpath prod- uct where system load is always prioritized over battery charging. due to excessive system load, there may not be suf?cient power to charge the battery beyond the trickle charge threshold voltage within the bad battery timeout period. in this case, the battery charger will falsely indicate a bad battery. system software may then reduce the load and reset the battery charger to try again. although very improbable, it is possible that a duty cycle reading could be taken at the bright-dim transition (low duty cycle to high duty cycle). when this happens the duty cycle reading will be precisely 50%. if the duty cycle reading is 50%, system software should disqualify it and take a new duty cycle reading. ntc thermistor the battery temperature is measured by placing a nega- tive temperature coef?cient (ntc) thermistor close to the battery pack. to use this feature, connect the ntc thermistor, r ntc , be- tween the ntc pin and ground and a resistor, r nom , from v bus to the ntc pin. r nom should be a 1% resistor with a value equal to the value of the chosen ntc thermistor at 25c (r25). a 100k thermistor is recommended since thermistor current is not measured by the LTC3556 and will have to be budgeted for usb compliance. the LTC3556 will pause charging when the resistance of the ntc thermistor drops to 0.54 times the value of r25 or approximately 54k. for vishay curve 1 thermistor, this corresponds to approximately 40c. if the battery charger is in constant-voltage (?oat) mode, the safety timer also pauses until the thermistor indicates a return to a valid temperature. as the temperature drops, the resistance of the ntc thermistor rises. the LTC3556 is also designed to pause charging when the value of the ntc thermistor increases to 3.25 times the value of r25. for vishay curve 1 this resistance, 325k, corresponds to approximately 0c. the hot and cold comparators each operation
LTC3556 19 3556p have approximately 3c of hysteresis to prevent oscillation about the trip point. grounding the ntc pin disables the ntc charge pausing function. thermal regulation to optimize charging time, an internal thermal feedback loop may automatically decrease the programmed charge current. this will occur if the die temperature rises to approximately 110c. thermal regulation protects the LTC3556 from excessive temperature due to high power operation or high ambient thermal conditions and allows the user to push the limits of the power handling capability with a given circuit board design without risk of damag- ing the LTC3556 or external components. the bene?t of the LTC3556 thermal regulation loop is that charge current can be set according to actual conditions rather than worst-case conditions with the assurance that the battery charger will automatically reduce the current in worst-case conditions. i 2 c interface the LTC3556 may receive commands from a host (mas- ter) using the standard i 2 c 2-wire interface. the timing diagram shows the timing relationship of the signals on the bus. the two bus lines, sda and scl, must be high when the bus is not in use. external pull-up resistors or current sources, such as the ltc1694 i 2 c accelerator, are required on these lines. the LTC3556 is a receive-only (slave) device. the i 2 c control signals, sda and scl are scaled internally to the dv cc supply. dv cc should be con- nected to the same power supply as the microcontroller generating the i 2 c signals. the i 2 c port has an undervoltage lockout on the dv cc pin. when dv cc is below approximately 1v, the i 2 c serial port is cleared and switching regulators 1 and 3 are set to full scale. bus speed the i 2 c port is designed to be operated at speeds of up to 400khz. it has built-in timing delays to ensure correct operation when addressed from an i 2 c compliant master device. it also contains input ?lters designed to suppress glitches should the bus become corrupted. start and stop condition a bus master signals the beginning of a communication to a slave device by transmitting a start condition. a start condition is generated by transitioning sda from high to low while scl is high. when the master has ?nished communicating with the slave, it issues a stop condition by transitioning sda from low to high while scl is high. the bus is then free for communication with another i 2 c device. byte format each byte sent to the LTC3556 must be eight bits long followed by an extra clock cycle for the acknowledge bit to be returned by the LTC3556. the data should be sent to the LTC3556 most signi?cant bit (msb) ?rst. acknowledge the acknowledge signal is used for handshaking between the master and the slave. an acknowledge (active low) generated by the slave (LTC3556) lets the master know that the latest byte of information was received. the acknowledge related clock pulse is generated by the master. the master releases the sda line (high) during the acknowledge clock cycle. the slave receiver must pull down the sda line during the acknowledge clock pulse so that it remains a stable low during the high period of this clock pulse. slave address the LTC3556 responds to only one 7-bit address which has been factory programmed to 0001001. the lsb of the address byte is 1 for read and 0 for write. this device is write only corresponding to an address byte of 00010010 (0 12). if the correct seven bit address is given but the r/w bit is 1, the LTC3556 will not respond. operation
LTC3556 20 3556p bus write operation the master initiates communication with the LTC3556 with a start condition and a 7-bit address followed by the write bit r/w = 0. if the address matches that of the LTC3556, the LTC3556 returns an acknowledge. the master should then deliver the most signi?cant data byte. again the LTC3556 acknowledges and the cycle is repeated for a total of one address byte and two data bytes. each data byte is transferred to an internal holding latch upon the return of an acknowledge. after both data bytes have been transferred to the LTC3556, the master may terminate the communication with a stop condition. alternatively, a repeat-start condition can be initiated by the master and another chip on the i 2 c bus can be addressed. this cycle can continue inde?nitely and the LTC3556 will remember the last input of valid data that it received. once all chips on the bus have been addressed and sent valid data, a global stop condition can be sent and the LTC3556 will update its command latch with the data that it had received. in certain circumstances the data on the i 2 c bus may become corrupted. in these cases the LTC3556 responds appropriately by preserving only the last set of complete data that it has received. for example, assume the LTC3556 has been successfully addressed and is receiving data when a stop condition mistakenly occurs. the LTC3556 will ignore this stop condition and will not respond until a new start condition, correct address, new set of data and stop condition are transmitted. likewise, with only one exception, if the LTC3556 was previously addressed and sent valid data but not updated with a stop, it will respond to any stop that appears on the bus, independent of the number of repeat-starts that have occurred. if a repeat-start is given and the LTC3556 successfully acknowledges its address and ? rst byte, it will not respond to a stop until both bytes of the new data have been received and acknowledged. operation table 2. i 2 c serial port mapping (defaults to 0xff00 in reset state or if dv cc = 0v) a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 switching regulator 1 voltage (see table 4) switching regulator 3 voltage (see table 4) disable battery charger switching regulator modes (see table 5) enable regulator 1 enable regulator 2 enable regulator 3 input current limit (see table 3) table 3. usb current limit settings b1 b0 usb setting 0 1 10x mode (wall 1a limit) 1 1 5x mode (usb 500ma limit) 0 0 1x mode (usb 100ma limit) 1 0 suspend table 4. switching regulator servo voltage a7 a6 a5 a4 switching regulator 1 servo voltage a3 a2 a1 a0 switching regulator 3 servo voltage 0000 0.425v 0001 0.450v 0010 0.475v 0011 0.500v 0100 0.525v 0101 0.550v 0110 0.575v 0111 0.600v 1000 0.625v 1001 0.650v 1010 0.675v 1011 0.700v 1100 0.725v 1101 0.750v 1110 0.775v 1111 0.800v table 5. switching regulator modes b6 b5 mode of (buck) switching regulators 1 and 2 mode of (buck-boost) switching regulator 3 0 0 pulse skip mode pwm mode 1 1 burst mode operation 0 1 forced burst mode operation burst mode operation 1 0 ldo mode
LTC3556 21 3556p disabling the i 2 c port the i 2 c serial port can be disabled by grounding the dv cc pin. in this mode, control automatically passes to the individual logic input pins enall and seq. however, considerable functionality is not available in this mode such as the ability to independently enable the three switching regulators and disable the battery charger. in addition, with the i 2 c port disabled, both programmable switching regulators default to a ?xed servo voltage of 0.8v, both 400ma bucks default to pulse skip mode, the 1a buck- boost defaults to pwm mode, and the usb input current limit defaults to 1x mode (100ma limit). pgoodall pin the pgoodall pin is an open-drain output used to in- dicate that all enabled switching regulators have reached their ?nal voltage. pgoodall remains low impedance until the last enabled regulator in the sequence reaches 92% of its regulation value. a 230ms delay is included to allow a system microcontroller ample time to reset itself. pgoodall may be used as a power-on reset to the microprocessor powered by one (or more) of the three regulated outputs. pgoodall is an open-drain output and requires a pull-up resistor to the input voltage of the monitoring microprocessor or another appropriate power source. 400ma step-down switching regulators the LTC3556 contains two 2.25mhz step-down (buck) constant-frequency current mode switching regulators. each buck regulator can provide up to 400ma of output current. both buck regulators can be programmed for a minimum output voltage of 0.8v and can be used to power a microcontroller core, microcontroller i/o, memory, disk drive or other logic circuitry. one of the buck regulators has i 2 c programmable set-points for on-the-?y power savings. both buck converters support 100% duty cycle operation (low dropout mode) when their input voltage drops very close to their output voltage. to suit a variety of applications, selectable mode functions can be used to trade off noise for ef?ciency. four modes are available to control the operation of the LTC3556s buck regulators. at moderate to heavy loads, the pulse skip mode provides the least noise switching solution. at lighter loads, either burst mode operation, forced burst mode operation or ldo mode may be selected. the buck regulators include soft-start to limit inrush current when powering on, short- circuit current protection and switch node slew limiting circuitry to reduce radiated emi. no external compensation components are required. the operating mode of the buck regulators can be set by i 2 c control and defaults to pulse skip mode if the i 2 c port is not used. both buck converters are enabled (along with the buck-boost) when the enall pin is asserted or each may be individually enabled by the i 2 c port. buck regulator 1 has a programmable feedback servo voltage via i 2 c control (which defaults to 800mv if the i 2 c port is not used) whereas buck regulator 2 has a ? xed feedback servo voltage of 800mv. the buck regulator input supplies v in1 and v in2 will generally be connected to the system load pin v out . buck regulator output voltage programming both buck regulators can be programmed for output voltages greater than 0.8v. the full-scale output voltage for each buck regulator is programmed using a resistor divider from the buck regulator output connected to the feedback pins (fb1 and fb2) such that: vv r r outx fbx =+ ? ? ? ? ? ? 1 2 1 where v fbx ranges from 0.425v to 0.8v for buck regula- tor 1 and v fbx is ?xed at 0.8v for buck regulator 2. see figure 4. typical values for r1 are in the range of 40k to 1m. the capacitor, c fb , cancels the pole created by feedback resis- tors and the input capacitance of the fbx pin and also helps to improve transient response for output voltages much operation v inx LTC3556 l swx r1 c out c fb v outx r2 3556 f04 fbx gnd figure 4. buck converter application circuit
LTC3556 22 3556p greater than 0.8v. a variety of capacitor sizes can be used for c fb but a value of 10pf is recommended for most ap- plications. experimentation with capacitor sizes between 2pf and 22pf may yield improved transient response. buck regulator operating modes the LTC3556s buck regulators include four possible op- erating modes to meet the noise/power needs of a variety of applications. in pulse skip mode, an internal latch is set at the start of every cycle which turns on the main p-channel mosfet switch. during each cycle, a current comparator compares the peak inductor current to the output of an error ampli?er. the output of the current comparator resets the internal latch which causes the main p-channel mosfet switch to turn off and the n-channel mosfet synchronous recti?er to turn on. the n-channel mosfet synchronous recti?er turns off at the end of the 2.25mhz cycle or if the current through the n-channel mosfet synchronous recti?er drops to zero. using this method of operation, the error ampli?er adjusts the peak inductor current to deliver the required output power. all necessary compensation is internal to the switching regulator requiring only a single ceramic output capacitor for stability. at light loads in pwm mode, the inductor current may reach zero on each pulse which will turn off the n-channel mosfet synchronous recti?er. in this case, the switch node (sw) goes high impedance and the switch node voltage will ring. this is discontinuous mode operation and is normal behavior for a switching regulator. at very light loads in pulse skip mode, the buck regulators will automatically skip pulses as needed to maintain output regulation. at high duty cycles (v outx > v inx /2) it is possible for the inductor current to reverse, causing the buck regulator to operate continuously at light loads. this is normal and regulation is maintained, but the supply current will increase to several milliamperes due to continuous switching. in forced burst mode operation, the buck regulators use a constant-current algorithm to control the inductor current. by controlling the inductor current directly and using a hysteretic control loop, both noise and switching losses are minimized. in this mode output power is limited. while in forced burst mode operation, the output capacitor is charged to a voltage slightly higher than the regulation point. the step-down converter then goes into sleep mode, during which the output capacitor provides the load cur rent. in sleep mode, most of the regulators circuitry is powered down, helping conserve battery power. when the output voltage drops below a predetermined value, the buck regulator circuitry is powered on and another burst cycle begins. the duration for which the buck regulator operates in sleep mode depends on the load current. the sleep time decreases as the load current increases. the maximum output current in forced burst mode operation is about 100ma for buck regulators 1 and 2. the buck regulators will not enter sleep mode if the maximum output current is exceeded in forced burst mode operation and the output will drop out of regulation. forced burst mode operation provides a signi?cant improvement in ef?ciency at light loads at the expense of higher output ripple when compared to pulse skip mode. for many noise-sensitive systems, forced burst mode operation might be undesirable at certain times (i.e., during a transmit or receive cycle of a wireless device), but highly desirable at others (i.e., when the device is in low power standby mode). the i 2 c port can be used to enable or disable forced burst mode operation at any time, offering both low noise and low power operation when they are needed. in burst mode operation, the buck regulator automati- cally switches between ?xed frequency pwm operation and hysteretic control as a function of the load current. at light loads, the buck regulators operate in hysteretic mode in much the same way as described for the forced burst mode operation. burst mode operation provides slightly less output ripple at the expense of slightly lower ef?ciency than forced burst mode operation. at heavy loads, the buck regulator operates in the same manner as pulse skip operation does at high loads. for applica- tions that can tolerate some output ripple at low output currents, burst mode operation provides better ef?ciency than pulse skip at light loads while still providing the full speci?ed output current of the buck regulator. finally, the buck regulators have an ldo mode that gives a dc option for regulating their output voltages. in ldo mode, the buck regulators are converted to linear regula- operation
LTC3556 23 3556p tors and deliver continuous power from their swx pins through their respective inductors. this mode gives the lowest possible output noise as well as low quiescent current at light loads. the buck regulators allow mode transition on the ?y, providing seamless transition between modes even under load. this allows the user to switch back and forth between modes to reduce output ripple or increase low current ef?ciency as needed. buck regulator in shutdown the buck regulators are in shutdown when not enabled for operation. in shutdown, all circuitry in the buck regulator is disconnected from the buck regulator input supply leaving only a few nanoamperes of leakage current. the buck regulator outputs are individually pulled to ground through a 10k resistor on the switch pins (sw1 and sw2) when in shutdown. buck regulator dropout operation it is possible for a buck regulators input voltage, v inx , to approach its programmed output voltage (e.g., a battery voltage of 3.4v with a programmed output voltage of 3.3v). when this happens, the pmos switch duty cycle increases until it is turned on continuously at 100%. in this dropout condition, the respective output voltage equals the buck regulators input voltage minus the voltage drops across the internal p-channel mosfet and the inductor. buck regulator soft-start operation soft-start is accomplished by gradually increasing the peak inductor current for each buck regulator over a 500s period. this allows each output to rise slowly, helping minimize the battery surge current. a soft-start cycle occurs whenever a given buck regulator is enabled, or after a fault condition has occurred (thermal shutdown or uvlo). a soft-start cycle is not triggered by changing operating modes. this allows seamless output operation when transitioning between forced burst mode, burst mode, pulse skip mode or ldo operation. buck regulator switching slew rate control the buck regulators contain new patent pending circuitry to limit the slew rate of the switch node (sw1 and sw2). this new circuitry is designed to transition the switch node over a period of a couple of nanoseconds, signi?cantly reducing radiated emi and conducted supply noise. low supply operation the LTC3556 incorporates an undervoltage lockout circuit on v out which shuts down both buck regulators (as well as the buck-boost) when v out drops below v outuvlo . this uvlo prevents unstable operation. buck-boost dc/dc switching regulator the LTC3556 contains a 2.25mhz constant-frequency volt- age mode buck-boost switching regulator. the regulator provides up to 1a of output load current. the buck-boost can be programmed to a minimum output voltage of 2.5v and can be used to power a microcontroller core, micro- controller i/o, memory, disk drive or other logic circuitry. when controlled by i 2 c, the buck-boost has programmable set-points for on-the-? y power savings. to suit a variety of applications, a selectable mode function allows the user to trade off noise for ef? ciency. two modes are available to control the operation of the LTC3556s buck-boost regula- tor. at moderate to heavy loads, the constant frequency pwm mode provides the least noise switching solution. at lighter loads burst mode operation may be selected. the full-scale output voltage is programmed by a user-supplied resistive divider returned to the fb3 pin. an error ampli? er compares the divided output voltage with a reference and adjusts the compensation voltage accordingly until the fb3 has stabilized to the selected reference voltage (0.425v to 0.8v). the buck-boost regulator also includes a soft-start to limit inrush current and voltage overshoot when powering on, short circuit current protection, and switch node slew limiting circuitry for reduced radiated emi. operation
LTC3556 24 3556p input current limit the input current limit comparator will shut the input pmos switch off once current exceeds 2.5a (typical). the 2.5a input current limit also protects against a grounded v out3 node. output overvoltage protection if the fb3 node were inadvertently shorted to ground, then the output would increase inde? nitely with the maximum current that could be sourced from v in3 . the LTC3556 protects against this by shutting off the input pmos if the output voltage exceeds 5.75v (typical). low output voltage operation when the output voltage is below 2.5v (typical) during startup, burst mode operation is disabled and switch d is turned off (allowing forward current through the well diode and limiting reverse current to 0ma). buck-boost regulator pwm operating mode in pwm mode the voltage seen at fb3 is compared to the selected reference voltage (0.425v to 0.8v). from the fb3 voltage an error ampli? er generates an error signal seen at v c3 . this error signal commands pwm waveforms that modulate switches a, b, c and d. switches a and b operate synchronously as do switches c and d. if v in3 is signi? cantly greater than the programmed v out3 , then the converter will operate in buck mode. in this case switches a and b will be modulated, with switch d always on (and switch c always off), to step down the input voltage to the programmed output. if v in3 is signi? cantly less than the programmed v out3 , then the converter will operate in boost mode. in this case switches c and d are modulated, with switch a always on (and switch b always off), to step up the input voltage to the programmed output. if v in3 is close to the programmed v out3 , then the converter will operate in 4-switch mode. in this mode the switches se- quence through the pattern of ad, ac, bd to either step the input voltage up or down to the programmed output. buck-boost regulator burst mode operation in burst mode operation, the buck-boost regulator uses a hysteretic fb3 voltage algorithm to control the output voltage. by limiting fet switching and using a hysteretic control loop, switching losses are greatly reduced. in this mode output current is limited to 50ma typical. while operating in burst mode operation, the output capacitor is charged to a voltage slightly higher than the regulation point. the buck-boost converter then goes into a sleep state, during which the output capacitor provides the load current. the output capacitor is charged by charging the inductor until the input current reaches 250ma typical and then discharging the inductor until the reverse current reaches 0ma typical. this process is repeated until the feedback voltage has charged to 6mv above the regulation point. in the sleep state, most of the regulators circuitry is powered down, helping to conserve battery power. when the feedback voltage drops 6mv below the regulation point, the switching regulator circuitry is powered on and another burst cycle begins. the duration for which the regulator sleeps depends on the load current and output capacitor value. the sleep time decreases as the load cur- rent increases. the maximum load current in burst mode operation is 50ma typical. the buck-boost regulator will not go to sleep if the current is greater than 50ma, and if the load current increases beyond this point while in burst mode operation the output will lose regulation. burst mode operation provides a signi? cant improvement in ef- ? ciency at light loads at the expense of higher output ripple when compared to pwm mode. for many noise-sensitive systems, burst mode operation might be undesirable at certain times (i.e., during a transmit or receive cycle of a wireless device), but highly desirable at others (i.e., when the device is in low power standby mode). the b6 and b5 bits of the i 2 c port are used to enable or disable burst mode operation at any time, offering both low noise and low power operation when they are needed. operation
LTC3556 25 3556p buck-boost regulator soft-start operation soft-start is accomplished by gradually increasing the reference voltage input to the error ampli? er over a 0.5ms (typical) period. this limits transient inrush currents during start-up because the output voltage is always in regula- tion. ramping the reference voltage input also limits the rate of increase in the v c3 voltage which helps minimize output overshoot during start-up. a soft-start cycle oc- curs whenever the buck-boost is enabled, or after a fault condition has occurred (thermal shutdown or uvlo). a soft-start cycle is not triggered by changing operating modes. this allows seamless operation when transitioning between burst mode operation and pwm mode. low supply operation the LTC3556 incorporates an undervoltage lockout circuit on v out (connected to v in3 ) which shuts down the buck- boost regulator when v out drops below 2.6v. this uvlo prevents unstable operation. operation applications information clprog resistor and capacitor as described in the high ef?ciency switching powerpath controller section, the resistor on the clprog pin deter- mines the average input current limit when the switching regulator is set to either the 1x mode (usb 100ma), the 5x mode (usb 500ma) or the 10x mode. the input cur- rent will be comprised of two components, the current that is used to drive v out and the quiescent current of the switching regulator. to ensure that the usb speci?cation is strictly met, both components of input current should be considered. the electrical characteristics table gives values for quiescent currents in either setting as well as current limit programming accuracy. to get as close to the 500ma or 100ma speci?cations as possible, a 1% resistor should be used. recall that i vbus = i vbusq + v clprog /r clpprog ? (h clprog +1). an averaging capacitor or an r-c combination is required in parallel with the clprog resistor so that the switching regulator can determine the average input current. this network also provides the dominant pole for the feedback loop when current limit is reached. to ensure stability, the capacitor on clprog should be 0.47f or larger. alternatively, faster transient response may be achieved with 0.1f in series with 8.2. choosing the powerpath inductor because the input voltage range and output voltage range of the power path switching regulator are both fairly nar- row, the LTC3556 was designed for a speci? c inductance value of 3.3h. some inductors which may be suitable for this application are listed in table 6. table 6. recommended inductors for powerpath controller inductor type l (h) max i dc (a) max dcr () size in mm (l w h) manufacturer lps4018 3.3 2.2 0.08 3.9 3.9 1.7 coilcraft www.coilcraft.com d53lc db318c 3.3 3.3 2.26 1.55 0.034 0.070 5.0 5.0 3.0 3.8 3.8 1.8 toko www.toko.com we-tpc type m1 3.3 1.95 0.065 4.8 4.8 1.8 wrth elektronik www.we-online.com cdrh6d12 cdrh6d38 3.3 3.3 2.2 3.5 0.0625 0.020 6.7 6.7 1.5 7.0 7.0 4.0 sumida www.sumida.com v bus and v out bypass capacitors the style and value of capacitors used with the LTC3556 determine several important parameters such as regulator control-loop stability and input voltage ripple. because the LTC3556 uses a step-down switching power supply from v bus to v out , its input current waveform contains high frequency components. it is strongly recommended that a low equivalent series resistance (esr) multilayer ceramic capacitor be used to bypass v bus . tantalum and aluminum capacitors are not recommended because of their high esr. the value of the capacitor on v bus directly controls the amount of input ripple for a given load cur- rent. increasing the size of this capacitor will reduce the input ripple.
LTC3556 26 3556p applications information to prevent large v out voltage steps during transient load conditions, it is also recommended that a ceramic capaci- tor be used to bypass v out . the output capacitor is used in the compensation of the switching regulator. at least 4f of actual capacitance with low esr are required on v out . additional capacitance will improve load transient performance and stability. multilayer ceramic chip capacitors typically have excep- tional esr performance. mlccs combined with a tight board layout and an unbroken ground plane will yield very good performance and low emi emissions. there are several types of ceramic capacitors available, each having considerably different characteristics. for example, x7r ceramic capacitors have the best voltage and temperature stability. x5r ceramic capacitors have apparently higher packing density but poorer performance over their rated voltage and temperature ranges. y5v ceramic capacitors have the highest packing density, but must be used with caution, because of their extreme nonlinear characteristic of capacitance vs voltage. the actual in-circuit capacitance of a ceramic capacitor should be measured with a small ac signal (ideally less than 200mv) as is expected in-circuit. many vendors specify the capacitance vs voltage with a 1v rms ac test signal and as a result overstate the capacitance that the capacitor will present in the application. using similar operating condi- tions as the application, the user must measure or request from the vendor the actual capacitance to determine if the selected capacitor meets the minimum capacitance that the application requires. 400ma step-down switching regulator inductor selection many different sizes and shapes of inductors are avail- able from numerous manufacturers. choosing the right inductor from such a large selection of devices can be overwhelming, but following a few basic guidelines will make the selection process much simpler. the buck converters are designed to work with inductors in the range of 2.2h to 10h. for most applications a 4.7h inductor is suggested for both buck regulators. larger value inductors reduce ripple current which improves output ripple voltage. lower value inductors result in higher ripple current and improved transient response time. to maximize ef?ciency, choose an inductor with a low dc resistance. for a 1.2v output, ef?ciency is reduced about 2% for 100m series resistance at 400ma load current, and about 2% for 300m series resistance at 100ma load current. choose an inductor with a dc current rating at least 1.5 times larger than the maximum load current to ensure that the inductor does not saturate during normal operation. if output short-circuit is a possible condition, the inductor should be rated to handle the maximum peak current speci?ed for the buck converters. different core materials and shapes will change the size/current and price/current relationship of an induc- tor. toroid or shielded pot cores in ferrite or permalloy materials are small and dont radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. inductors that are very thin or have a very small volume typically have much higher core and dcr losses, and will not give the best ef- ?ciency. the choice of which style inductor to use often depends more on the price vs size, performance and any radiated emi requirements than on what the LTC3556 requires to operate. the inductor value also has an effect on forced burst and burst mode operations. lower inductor values will cause the burst mode and forced burst mode switching frequencies to increase. table 7 shows several inductors that work well with the LTC3556s buck regulators. these inductors offer a good compromise in current rating, dcr and physical size. consult each manufacturer for detailed information on their entire selection of inductors. table 7. recommended inductors for 400ma step-down switching regulators nductor type l (h) max i dc (a) max dcr () size in mm (l w h) manufacturer de2818c 4.7 1.25 0.072* 3.0 2.8 1.8 toko www.toko.com de2812c 4.7 1.15 0.13* 3.0 2.8 1.2 cdrh3d16 4.7 0.9 0.11 4.0 4.0 1.8 sumida www.sumida.com sd3118 4.7 1.3 0.162 3.1 3.1 1.8 cooper www.cooperet. com sd3112 4.7 0.8 0.246 3.1 3.1 1.2 lps3015 4.7 1.1 0.2 3.0 3.0 1.5 coilcraft www.coilcraft.com *typical dcr
LTC3556 27 3556p applications information 400ma step-down switching regulator input/output capacitor selection low esr (equivalent series resistance) mlcc capacitors should be used at both buck regulator outputs as well as at each buck regulator input supply (v in1 and v in2 ). only x5r or x7r ceramic capacitors should be used because they retain their capacitance over wider voltage and temperature ranges than other ceramic types. a 10f output capaci- tor is suf?cient for most applications. for good transient response and stability the output capacitor should retain at least 4f of capacitance over operating temperature and bias voltage. each buck regulator input supply should be bypassed with a 1f capacitor. consult with capacitor manufacturers for detailed information on their selection and speci?cations of ceramic capacitors. many manufac- turers now offer very thin (<1mm tall) ceramic capacitors ideal for use in height-restricted designs. table 8 shows a list of several ceramic capacitor manufacturers. table 8. recommended ceramic capacitor manufacturers avx www.avxcorp.com murata www.murata.com taiyo yuden www.t-yuden.com vishay siliconix www.vishay.com tdk www.tdk.com buck-boost regulator inductor selection inductor selection criteria for the buck-boost are similar to those given for the 400ma step-down switching regulators. the buck-boost converter is designed to work with induc- tors in the range of 1h to 5h. for most applications a 2.2h inductor will suf? ce. choose an inductor with a dc current rating at least 2 times larger than the maximum load current to ensure that the inductor does not saturate during normal operation. if output short circuit is a pos- sible condition, the inductor should be rated to handle the maximum peak current speci? ed for the buck-boost converter. table 9 shows several inductors that work well with the LTC3556s buck-boost regulator. these inductors offer a good compromise in current rating, dcr and physical size. consult each manufacturer for detailed information on their entire selection of inductors. table 9. recommended inductors for buck-boost regulator inductor type l (h) max i dc (a) max dcr () size in mm (l w h) manufacturer lps4018 3.3 2.2 2.2 2.5 0.08 0.07 3.9 3.9 1.7 3.9 3.9 1.7 coilcraft www.coilcraft.com d53lc 2.0 3.25 0.02 5.0 5.0 3.0 toko www.toko.com 7440430022 2.2 2.5 0.028 4.8 4.8 2.8 wrth-elektronik www.we-online.com cdrh4d22/ hp 2.2 2.4 0.044 4.7 4.7 2.4 sumida www.sumida.com sd14 2.0 2.56 0.045 5.2 5.2 1.45 cooper www.cooperet.com buck-boost regulator input/output capacitor selection low esr mlcc capacitors should also be used at both the buck-boost regulator output (v out3 ) and the buck-boost regulator input supply (v in3 ). again, only x5r or x7r ce- ramic capacitors should be used because they retain their capacitance over wider voltage and temperature ranges than other ceramic types. a 22f output capacitor is suf- ? cient for most applications. the buck-boost regulator input supply should be bypassed with a 2.2f capacitor. refer to table 8 for recommended ceramic capacitor manufacturers. buck-boost regulator output voltage programming the buck-boost regulator can be programmed for output voltages greater than 2.5v and less than 5.5v. the full-scale output voltage is programmed using a resistor divider from the v out3 pin connected to the fb3 pin such that: vv r r out fb 33 1 2 1 =+ ? ? ? ? ? ? where v fb3 ranges from 0.425v to 0.8v.
LTC3556 28 3556p closing the feedback loop the LTC3556 incorporates voltage mode pwm control. the control to output gain varies with operation region (buck, boost, buck-boost), but is usually no greater than 20. the output ? lter exhibits a double-pole response given by: f lc hz filter pole out _ ?? ? = 1 2 where c out is the output ? lter capacitor. the output ? lter zero is given by: f rc hz filter zero esr out _ ?? ? = 1 2 where r esr is the capacitor equivalent series resistance. a troublesome feature in boost mode is the right-half plane zero (rhp), and is given by: f v ilv hz rhpz in out out = 2 2? ? ? ? the loop gain is typically rolled off before the rhp zero frequency. a simple type i compensation network (as shown in figure 5) can be incorporated to stabilize the loop but at the cost of reduced bandwidth and slower transient response. to ensure proper phase margin, the loop must cross unity-gain a decade before the lc double pole. the unity-gain frequency of the error ampli? er with the type i compensation is given by: f rcp hz ug = 1 211 ?? ? most applications demand an improved transient response to allow a smaller output ? lter capacitor. to achieve a higher bandwidth, type iii compensation is required. two zeros are required to compensate for the double-pole response. type iii compensation also reduces any v out3 overshoot at start-up. the compensation network depicted in figure 6 yields the transfer function: v vrcc sr c s r r c c out 3 3 1 11 2 1221 133 = + +++ () ? ()[()] s ssrcc src 1212133 + ? ? ? ? + (|| )( ) a type iii compensation network attempts to introduce a phase bump at a higher frequency than the lc double pole. this allows the system to cross unity gain after the lc double pole, and achieve a higher bandwidth. while attempting to cross over after the lc double pole, the system must still cross over before the boost right-half plane zero. if unity gain is not reached suf? ciently before the right-half plane zero, then the C180 of phase lag from applications information 7 C + error amp 0.8v r1 r2 3556 f05 fb3 8 v c3 c p1 v out3 figure 5. error ampli? er with type i compensation 7 C + error amp 0.8v r1 r3 c3 r fb 3556 f06 fb3 8 v c3 c2 c1 r2 v out3 figure 6. error ampli? er with type iii compensation
LTC3556 29 3556p the lc double pole combined with the C90 of phase lag from the right-half plane zero will result in negating the phase bump of the compensator. the compensator zeros should be placed either before or only slightly after the lc double pole such that their positive phase contributions offset the C180 that occurs at the ? lter double pole. if they are placed at too low of a frequency, they will introduce too much gain to the system and the crossover frequency will be too high. the two high frequency poles should be placed such that the system crosses unity gain during the phase bump introduced by the zeros and before the boost right-half plane zero and such that the compensator bandwidth is less than the bandwidth of the error amp (typically 900khz). if the gain of the compensation network is ever greater than the gain of the error ampli? er, then the error ampli? er no longer acts as an ideal op amp, and another pole will be introduced at the same point. recommended type iii compensation components for a 3.3v output: r1: 324k r fb : 105k c1: 10pf r2: 15k c2: 330pf r3: 121k c3: 33pf c out : 22f l out : 2.2h over-programming the battery charger the usb high power speci?cation allows for up to 2.5w to be drawn from the usb port (5v 500ma). the powerpath switching regulator transforms the voltage at v bus to just above the voltage at bat with high ef?ciency, while limiting power to less than the amount programmed at clprog. in some cases the battery charger may be programmed (with the prog pin) to deliver the maximum safe charging current without regard to the usb speci?cations. if there is insuf?cient current available to charge the battery at the programmed rate, the powerpath regulator will reduce charge current until the system load on v out is satis?ed and the v bus current limit is satis?ed. programming the battery charger for more current than is available will not cause the average input current limit to be violated. it will merely allow the battery charger to make use of all available power to charge the battery as quickly as possible, and with minimal power dissipation within the battery charger. alternate ntc thermistors and biasing the LTC3556 provides temperature quali?ed charging if a grounded thermistor and a bias resistor are connected to ntc. by using a bias resistor whose value is equal to the room temperature resistance of the thermistor (r25) the upper and lower temperatures are pre-programmed to approximately 40c and 0c, respectively (assuming a vishay curve 1 thermistor). the upper and lower temperature thresholds can be ad- justed by either a modi?cation of the bias resistor value or by adding a second adjustment resistor to the circuit. if only the bias resistor is adjusted, then either the upper or the lower threshold can be modi?ed but not both. the other trip point will be determined by the characteristics of the thermistor. using the bias resistor in addition to an adjustment resistor, both the upper and the lower tempera- ture trip points can be independently programmed with the constraint that the difference between the upper and lower temperature thresholds cannot decrease. examples of each technique follow. ntc thermistors have temperature characteristics which are indicated on resistance-temperature conversion tables. the vishay-dale thermistor nths0603n011-n1003f, used applications information
LTC3556 30 3556p in the following examples, has a nominal value of 100k and follows the vishay curve 1 resistance-temperature characteristic. in the explanation below, the following notation is used. r25 = value of the thermistor at 25c r ntc|cold = value of thermistor at the cold trip point r ntc|hot = value of thermistor at the hot trip point r cold = ratio of r ntc|cold to r25 r hot = ratio of r ntc|cold to r25 r nom = primary thermistor bias resistor (see figure 7a) r1 = optional temperature range adjustment resistor (see figure 7b) the trip points for the LTC3556s temperature quali?cation are internally programmed at 0.349 ? v bus for the hot threshold and 0.765 ? v bus for the cold threshold. therefore, the hot trip point is set when: r rr vv ntc hot nom ntc hot bus bus | | ?.? + = 0 349 and the cold trip point is set when: r rr vv ntc cold nom ntc cold bus bus | | ?.? + = 0 765 solving these equations for r ntc|cold and r ntc|hot results in the following: r ntc|hot = 0.536 ? r nom and r ntc|cold = 3.25 ? r nom by setting r nom equal to r25, the above equations result in r hot = 0.536 and r cold = 3.25. referencing these ratios to the vishay resistance-temperature curve 1 chart gives a hot trip point of about 40c and a cold trip point of about 0c. the difference between the hot and cold trip points is approximately 40c. by using a bias resistor, r nom , different in value from r25, the hot and cold trip points can be moved in either direction. the temperature span will change somewhat due applications information to the nonlinear behavior of the thermistor. the following equations can be used to easily calculate a new value for the bias resistor: r r r r r r nom hot nom cold = = 0 536 25 325 25 . ? . ? where r hot and r cold are the resistance ratios at the de- sired hot and cold trip points. note that these equations are linked. therefore, only one of the two trip points can be chosen, the other is determined by the default ratios designed in the ic. consider an example where a 60c hot trip point is desired. from the vishay curve 1 r-t characteristics, r hot is 0.2488 at 60c. using the above equation, r nom should be set to 46.4k. with this value of r nom , the cold trip point is about 16c. notice that the span is now 44c rather than the previous 40c. this is due to the decrease in tem- perature gain of the thermistor as absolute temperature increases. the upper and lower temperature trip points can be inde- pendently programmed by using an additional bias resistor as shown in figure 7b. the following formulas can be used to compute the values of r nom and r1: r rr r rrr nom cold hot nom hot = = C . ? .? C ? 2 714 25 1 0 536 r r25 for example, to set the trip points to 0c and 45c with a vishay curve 1 thermistor choose: rkk nom == 3 266 0 436 8 2 714 100 104 2 .C. . ?. the nearest 1% value is 105k. r1 = 0.536 ? 105k C 0.4368 ? 100k = 12.6k the nearest 1% value is 12.7k. the ?nal solution is shown in figure 7b and results in an upper trip point of 45c and a lower trip point of 0c.
LTC3556 31 3556p applications information C + C + r nom 100k r ntc 100k ntc 0.017v ? v bus ntc_enable 3556 f07a LTC3556 ntc block too_cold too_hot 0.765 ? v bus 0.349 ? v bus C + 3 v bus v bus t (7a) (7b) figure 7. ntc circuits C + C + r nom 105k r ntc 100k r1 12.7k ntc v bus v bus 0.017 ? v bus ntc_enable 3556 f07b too_cold too_hot 0.765 ? v bus 0.349 ? v bus C + 3 LTC3556 ntc block t
LTC3556 32 3556p applications information usb inrush limiting when a usb cable is plugged into a portable product, the inductance of the cable and the high-q ceramic input capacitor form an l-c resonant circuit. if the cable does not have adequate mutual coupling or if there is not much impedance in the cable, it is possible for the voltage at the input of the product to reach as high as twice the usb voltage (~10v) before it settles out. to prevent excessive voltage from damaging the LTC3556 during a hot insertion, it is best to have a low voltage coef?cient capacitor at the v bus pin to the LTC3556. this is achievable by selecting an mlcc capacitor that has a higher voltage rating than that required for the application. for example, a 16v, x5r, 10f capacitor in a 1206 case would be a more conservative choice than a 6.3v, x5r, 10f capacitor in a smaller 0805 case. the size of the input overshoot will be determined by the q of the resonant tank circuit formed by c in and the input lead inductance. it is recommended to measure the input ringing with the selected components to verify compliance with the absolute maximum speci? cations. alternatively, the following soft connect circuit (figure 8) can be employed. in this circuit, capacitor c1 holds mp1 off when the cable is ?rst connected. eventually c1 begins to charge up to the usb input voltage applying increasing gate support to mp1. the long time constant of r1 and c1 prevent the current from building up in the cable too fast thus dampening out any resonant overshoot. printed circuit board layout considerations in order to be able to deliver maximum current under all conditions, it is critical that the exposed pad on the backside of the LTC3556 package be soldered to the pc board ground. failure to make thermal contact between the exposed pad on the backside of the package and the copper board will result in higher thermal resistances. furthermore, due to its high frequency switching circuitry, it is imperative that the input capacitors, inductors and output capacitors be as close to the LTC3556 as possible and that there be an unbroken ground plane under the LTC3556 and all of its external high frequency compo- nents. high frequency currents such as the v bus , v in1 , v in2 and v in3 currents on the LTC3556, tend to ?nd their way along the ground plane in a myriad of paths ranging from directly back to a mirror path beneath the incident path on the top of the board. if there are slits or cuts in the ground plane due to other traces on that layer, the current will be forced to go around the slits. if high frequency currents are not allowed to ?ow back through their natural least-area path, excessive voltage will build up and radiated emissions will occur. there should be a group of vias under the grounded backside of the pack- age leading directly down to an internal ground plane. to minimize parasitic inductance, the ground plane should be on the second layer of the pc board. r1 40k 5v usb input 3556 f08 c1 100nf c2 10f mp1 si2333 usb cable v bus gnd LTC3556 figure 8. usb soft connect circuit
LTC3556 33 3556p applications information the gate pin for the external ideal diode controller has extremely limited drive current. care must be taken to minimize leakage to adjacent pc board traces. 100na of leakage from this pin will introduce an offset to the 15mv ideal diode of approximately 10mv. to minimize leakage, the trace can be guarded on the pc board by surrounding it with v out connected metal, which should generally be less that one volt higher than gate. when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3556. 1. are the capacitors at v bus , v in1 , v in2 and v in3 as close as possible to the LTC3556? these capacitors provide the ac current to the internal power mosfets and their drivers. minimizing inductance from these capacitors to the LTC3556 is a top priority. 2. are c out and l1 closely connected? the (C) plate of c out returns current to the gnd plane, and then back to c in . 3. keep sensitive components away from the sw pins. battery charger stability considerations the LTC3556s battery charger contains both a constant- voltage and a constant-current control loop. the constant- voltage loop is stable without any compensation when a battery is connected with low impedance leads. excessive lead length, however, may add enough series inductance to require a bypass capacitor of at least 1f from bat to gnd. furthermore, when the battery is disconnected, a 4.7f capacitor in series with a 0.2 to 1 resistor from bat to gnd is required to keep ripple voltage low. high value, low esr multilayer ceramic chip capacitors reduce the constant-voltage loop phase margin, possibly resulting in instability. ceramic capacitors up to 22f may be used in parallel with a battery, but larger ceramics should be decoupled with 0.2 to 1 of series resistance. in constant-current mode, the prog pin is in the feed- back loop rather than the battery voltage. because of the additional pole created by any prog pin capacitance, capacitance on this pin must be kept to a minimum. with no additional capacitance on the prog pin, the battery charger is stable with program resistor values as high as 25k. however, additional capacitance on this node reduces the maximum allowed program resistor. the pole frequency at the prog pin should be kept above 100khz. therefore, if the prog pin has a parasitic capacitance, c prog , the following equation should be used to calculate the maximum resistance value for r prog : r khz c prog prog 1 2 100 ?? 3556 f09 figure 9. higher frequency ground currents follow their incident path. slices in the ground plane cause high voltage and increased emissions
LTC3556 34 3556p typical application 11 + 26 25 24 23 29 21 22 mp1 c2 22f li-ion 510 to other loads 324k 121k 105k red 2.5v to 3.3v 1a 1.8v 400ma microprocessor por 0.8v to 1.6v 400ma l1 3.3h l2 2.2h sw v bus 3 t ntc 20 prog 2 clprog 100k 12 ltc3555 v out3 v c3 7 14 8 1 fb3 swcd3 9 swab3 ldo3v3 10 dv cc 13,16 28 27 2 i 2 c (scl, sda) v out bat gnd chrg gate 2.2f 330pf 15k 1f 1f 22f v in3 18 10pf 1.02m c1: murata grm21br61a106ke19 c2: tdk c2012x5r0j226m l1: coilcraft lps4018-332lm l2: coilcraft lps4018-222mlc l3, l4: toko 1098as-4r7m mp1: siliconix si2333 806k 19 l3 4.7h sw2 17 fb2 i/o core 10f 33pf v in2 enall seq 5 10pf 806k 806k 4 l4 4.7h sw1 6 fb1 10f 3556 ta02 v in1 15 pgoodall hdd 3.01k 2k 0.1f 8.25 c1 10f usb/wall 4.5v to 5.5v 1f pushbutton microcontroller 10k 10pf watchdog microcontroller operation
LTC3556 35 3556p information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description ufd package 28-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1712 rev b) 4.00 0.10 (2 sides) 2.50 ref 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 27 28 1 2 bottom viewexposed pad 3.50 ref 0.75 0.05 r = 0.115 typ r = 0.05 typ pin 1 notch r = 0.20 or 0.35 s 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 C 0.05 (ufd28) qfn 0506 rev b recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 2.50 ref 3.50 ref 4.10 0.05 5.50 0.05 2.65 0.05 3.10 0.05 4.50 0.05 package outline 2.65 0.10 3.65 0.10 3.65 0.05
LTC3556 36 3556p linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2007 lt 1207 ? printed in usa related parts typical application pushbutton start with automatic sequencing, reverse input voltage protection and 10 second push and hold hard shutdown 12 25 10 mp1 usb connector v out3 7 8 fb3 v c3 15 pgoodall 9 swab3 14 swcd3 4 sw1 v bus LTC3556 dv cc 1 ldo3v3 28 27 1m mn1 enall seq 29 gnd mn1: 2n7002 mp1: siliconix si2333ds 0.1f 6 fb1 13,16 i 2 c (scl, sda) 10f 1f 1k 4.7k 10k 10f 19 2 sw2 17 3556 ta03 fb2 10f memory core i/o scl sda send i 2 c code: 0x12ff1c once power is detected part number description comments ltc3455 dual dc/dc converter with usb power manager and li-ion battery charger seamless transition between input power sources: li-ion battery, usb and 5v wall adapter. two high ef?ciency dc/dc converters: up to 96%. full featured li-ion battery charger with accurate usb current limiting (500ma/100ma). pin selectable burst mode operation. hot swap tm output for sdio and memory cards. 24-lead 4mm 4mm qfn package ltc3456 2-cell, multi-output dc/dc converter with usb power manager seamless transition between 2-cell battery, usb and ac wall adapter input power sources. main output: fixed 3.3v output, core output: adjustable from 0.8v to v batt(min) . hot swap output for memory cards. power supply sequencing: main and hot swap accurate usb current limiting. high frequency operation: 1mhz. high ef?ciency: up to 92%. 24-lead 4mm 4mm qfn package ltc3552 standalone linear li-ion battery charger with adjustable output dual synchronous buck converter synchronous buck converter, ef?ciency: >90%, adjustable outputs at 800ma and 400ma, charge current programmable up to 950ma, usb compatible, 16-lead 5mm 3mm dfn package ltc3555/ ltc3555-1 high ef? ciency usb power manager plus triple step-down dc/dc maximizes available power from usb port, bat-track, instant on operation, 1.5a max charge current, 180m ideal diode with <50m option, 3.3v/25ma always-on ldo, three synchronous buck regulators (400ma/400ma/1a), 4mm 5mm qfn28 package ltc3557/ ltc3557-1 linear usb power manager with li-ion/ polymer charger and triple synchronous buck converter complete multifunction assp: linear power manager and three buck regulators charge current programmable up to 1.5a from wall adapter input, thermal regulation, synchronous buck ef?ciency: >95%, adj outputs: 0.8v to 3.6v at 400ma/400ma/600ma bat-track adaptive output control, 200m ideal diode, 4mm 4mm qfn28 package ltc4085 linear usb power manager with ideal diode controller and li-ion charger charges single cell li-ion batteries directly from a usb port, thermal regulation, 200m ideal diode with <50m option, 4mm 3mm dfn14 package ltc4088/ ltc4088-1 high ef?ciency usb power manager and battery charger maximizes available power from usb port, bat-track, instant on operation, 1.5a max charge current, 180m ideal diode with <50m option, 3.3v/25ma always-on ldo, 4mm 3mm dfn14 package hot swap is a trademark of linear technology corporation.

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